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| CY22800 Universal Programmable Clock Generator (UPCG) Features * Spread Spectrum, VCXO, and Frequency Select * Input frequency range: -- Crystal: 8-30 MHz -- CLKIN: 0.5-100 MHz * Output frequency: * * * * -- LVCMOS: 1-200 MHz Integrated phase-locked loop Low jitter, high accuracy outputs 3.3V operation 8-pin SOIC package Benefits * Make inventory of only one device, CY22800, to use in various applications such as HDTV, STB, DVDR, etc. * Multiple predefined configurations that can be programmed into a single chip * Eliminates the need for expensive and difficult to use higher-order crystal * High-performance PLL tailored for multiple applications * Meets critical timing requirements in complex system designs * Enables application compatibility * Allows up to three different frequency selects Logic Block Diagram Pin Configuration CY22800 8-pin SOIC XIN/CLKIN XOUT VCXO FS2 FS1 FS0 OSC Q VCO P CLKC OUTPUT DIVIDER XIN/CLKIN 1 2 3 4 8 7 6 5 XOUT CLKC/FS2/VSS CLKA/FS0 CLKB/FS1 CLKB CLKA VDD FS0/VCXO VSS PLL (with modulation control) VDD VSS Pin Description Name XIN VDD FS0/VCXO VSS CLKB/FS1 CLKA/FS0 CLKC/FS2/VSS XOUT Pin Number 1 2 3 4 5 6 7 8 Description Reference Input; Crystal or External Clock 3.3V Voltage Supply Frequency Select 0/VCXO Analog Control Voltage[1] Ground Clock Output B/Frequency Select 1[1] Clock Output A/Frequency Select 0[1] Clock Output C/Frequency Select 2/VSS[1] Reference Output (No Connect when the reference is a clock) Note 1. Pin definition changes for different configurations. Refer to the specific one-page data sheet for more details. Cypress Semiconductor Corporation Document #: 001-07704 Rev. ** * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised July 14, 2006 CY22800 General Description The CY22800 is a multi-function clock generator that supports various applications in consumer and communications markets. The device uses the Cypress proprietary PLL along with Spread Spectrum and VCXO technology to make it one of the most versatile clock synthesizer in the market place. The CY22800 is a field-programmable synthesizer that can be programmed using an easy-to-use programmer dongle, CY36800, with one of many predefined configuration files for fast sample generation of prototype builds. The CY22800 is a reprogrammable device that can be programmed up to five thousand times. The latest configurations available for this device are summarized in Table 1. VCXO One of the key components of the CY22800 device is the VCXO. The VCXO is used to "pull" the reference crystal higher or lower in order to lock the system frequency to an external source. This is ideal for applications where the output frequency needs to track along with an external reference frequency that is constantly shifting. A special pullable crystal must be used in order to have adequate VCXO pull range. Pullable Crystal specifications are included in this data sheet. VCXO Profile Figure 1 shows an example of what a VCXO profile looks like. The analog voltage input is on the X-axis and the PPM range is on the Y-axis. An increase in the VCXO input voltage results in a corresponding increase in the output frequency. This has the effect of moving the PPM from a negative to positive offset. Figure 1. VCXO Profile 200 150 100 Tuning [ppm] 50 0 -50 -100 -150 -200 VCXO input [V] 0 0.5 1 1.5 2 2.5 3 3.5 Spread Spectrum Clock Generation (SSCG) The CY22800 is capable of generating Spread Spectrum Clocks (SSCG) for the purpose of reducing EMI found in today's high-speed digital electronic systems. The device uses proprietary Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. By modulating the frequency of the clock, the measured EMI at the fundamental and harmonic frequencies is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency (EMC) requirements and improve time-to-market without degrading system performance. The CY22800 uses a preprogrammed configuration of memory arrays to synthesize output frequency and offers eight different spread percentages (refer to Table 1 - Code numbers -015 to -022), and an additional option to turn the spread on and off. For the above-mentioned configurations, the modulation frequency varies with the reference frequency as follows: f mod = f ref 1000 Document #: 001-07704 Rev. ** Page 2 of 8 CY22800 Table 1. CY22800 Configurations Document #: 001-07704 Rev. ** Page 3 of 8 CY22800 Cypress offers a wide range of programmable clock synthesizers that can be used to generate any other frequencies not covered by the CY22800. Table 2 summarizes all Cypress programmable devices including CY22800. Table 2. Cypress Programmable Clocks[2] Part # CY22800 CY22050 CY22150 CY25100 CY25200 CY241V08 CY22392 CY22381 CY22393 CY22394/5 CY22388/89/91 No. of PLL 1 1 1 1 1 1 3 3 3 3 4 Input Freq. 0.5-100 1-133 1-133 8-166 3-166 27/13.5 1-166 1-166 1-166 1-166 1-100 Output Freq. 1-200 0.08-200 0.08-200 3-200 3-200 27/13.5 1-200 1-200 1-200 1-200 4.2-166 Package 8-SOIC 16-TSSOP 16-TSSOP 8-SOIC/TSSOP 16-TSSOP 8-SOIC 16-TSSOP 8-SOIC 16-TSSOP 16-TSSOP 16/20-TSSOP, 32-QFN No. of Outputs up to 3 up to 6 up to 6 up to 2 up to 6 up to 2 up to 6 up to 3 up to 6 up to 5 up to 8 Spread Spectrum Yes No No Yes Yes No No No No No No VCXO Yes No No No No Yes No No No No Yes I2C No No Yes No No No No No Yes No No Note 2. The CY3672 programmer can be used to program all Cypress chips. Refer to the CY3672 data sheet for programming procedures. Document #: 001-07704 Rev. ** Page 4 of 8 CY22800 Absolute Maximum Conditions Parameter VDD TS TJ Supply Voltage Storage Temperature Junction Temperature Digital Inputs Digital Outputs referred to VDD Electro-Static Discharge Description Min. -0.5 -65 - VSS - 0.3 VSS - 0.3 2 Max. 4.6 125 125 VDD + 0.3 VDD + 0.3 - Unit V C C V V kV Recommended Operating Conditions Parameter VDD TA CLOAD fREF[3] tPU Operating Voltage Ambient Temperature Max. Load Capacitance on the CLK output Reference Frequency Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Description Min. 3.14 0 - 0.5 0.05 Typ. 3.3 - - - - Max. 3.47 70 15 100 500 Unit V C pF MHz ms Pullable Crystal Specifications for VCXO Application ONLY Parameter CLNOM R1 R3/R1 DL F3SEPHI F3SEPLO C0 C0/C1 C1 Crystal Load Capacitance Equivalent Series Resistance Ratio of Third Overtone Mode ESR to Fundamental Mode ESR. Ratio used because typical R1 values are much less than the maximum spec Crystal Drive Level. No external series resistor assumed Third overtone separation from 3*FNOM (High Side) Third overtone separation from 3*FNOM (Low Side) Crystal shunt capacitance Ratio of Shunt to motional capacitance Crystal motional capacitance 180 14.4 - 18 Name Min. - - 3 - 300 - Typ. 14 - - 0.5 - - Max. - 25 - 2 - -150 7 250 21.6 pF Unit pF - mW ppm ppm pF Recommended Crystal Specifications for ALL other Applications Parameter FNOM CLNOM R1 DL Name Nominal Crystal Frequency Nominal Load Capacitance Equivalent Series Resistance (ESR) Crystal Drive Level Fundamental mode No external series resistor assumed Description Parallel resonance, fundamental mode, and AT cut Min. 8 - - - Typ. - 12 35 0.5 Max. 30 - 50 2 Unit MHz pF mW Note 3. Configuration dependent, see the one-page document. Document #: 001-07704 Rev. ** Page 5 of 8 CY22800 DC Electrical Specifications Parameter IOH IOL CIN1 CIN2 IIH IIL fXO VVCXO VIH VIL Name Output High Current Output Low Current Input Capacitance Input Capacitance Input High Current Input Low Current VCXO Pullability Range VCXO Input Range Input High Voltage Input Low Voltage CMOS levels, 70% of VDD CMOS levels, 30% of VDD Description VOH = VDD - 0.5, VDD = 3.3V (source) VOL = 0.5, VDD = 3.3V (sink) All input pins except XIN and XOUT XIN and XOUT pins VIH = VDD VIL = 0V Min. 12 12 - - - - 150 0 0.7 - Typ. 24 24 - 24 5 - - - - - VDD - 0.3 Max. - - 7 - 10 50 Unit mA mA pF pF A A ppm V VDD VDD AC Electrical Characteristics (VDD = 3.3V) Parameter DC t3 t4 t10 Name Output Duty Cycle Rising Edge Slew Rate Falling Edge Slew Rate PLL Lock Time Description Duty Cycle is defined in Figure 3, 50% of VDD Output Clock Rise Time, 20% - 80% of VDD Output Clock Fall Time, 80% - 20% of VDD Min. 45 0.8 0.8 - Typ. 50 1.4 1.4 - Max. 55 - - 3 Unit % V/ns V/ns ms Test Circuit Figure 2. Test Circuit Diagram VDD 0.1F OUTPUTS CLKout CLOAD CLK Figure 4. Rise and Fall Time Definitions t3 80% 20% t4 GND Figure 3. Duty Cycle Definition; DC = t2/t1 t1 t2 CLK 50% 50% Document #: 001-07704 Rev. ** Page 6 of 8 CY22800 Ordering Information Ordering Code CY22800FXC Package Type 8-Pin SOIC Operating Range Commercial Operating Voltage 3.3V Package Diagram Figure 5. 8-Lead (150-Mil) SOIC S8 51-85066-*C All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-07704 Rev. ** Page 7 of 8 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY22800 Document History Page Document Title: CY22800 Universal Programmable Clock Generator (UPCG) Document Number: 001-07704 REV. ** ECN NO. 478688 Issue Date See ECN Orig. of Change KKVTMP New data sheet Description of Change Document #: 001-07704 Rev. ** Page 8 of 8 |
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